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From devices, to architectures, to trust
Neuromorphic devices and circuits
We develop and exploit beyond-CMOS devices to implement AI primitives — synaptic plasticity, neuronal spiking — directly in hardware. Memristors are the main focus: they store data and perform analog multiplication in the same element, collapsing the von Neumann bottleneck that dominates the energy cost of load–compute–store architectures. Most of our work integrates memristors into neuron, synapse, and training circuits, alongside semi-empirical modeling and SPICE model development. We're also interested in three- and four-terminal memristors and biristors for spiking neuron implementation.
Brain-inspired architectures and algorithms
Device randomness is usually treated as a defect. We treat it as a resource. A recurring theme is random projection networks — networks with random weights and topologies that fit a target function by pairing linear regression with a large random feature space, and that need far fewer hardware resources than conventional alternatives. We also design training algorithms tailored to learning in hardware, including stochastic logic that cuts the overhead of gradient computation. Related interests: spiking neural network hardware, energy-harvesting AI, and perturbation-based learning.
Trustworthy AI hardware
AI is moving into size-, weight-, and power-constrained places — wearables, phones, robots, UAVs, satellites — and custom neuromorphic hardware is following it there. The security questions have not kept up. Deep networks are famously vulnerable to adversarial attack, yet almost nothing is known about how hardware-specific characteristics (low precision, process variation, defects, noise) change that vulnerability. We work on three fronts: modeling how hardware faults and noise affect adversarial susceptibility, designing adversarially robust training for neuromorphic systems, and developing new attacks that exploit hardware-specific attributes.